Data may be transferred between host computers and peripheral storage devices in accordance with various standards. In addition, various methods of structuring the transfer of commands and data may be utilized.
As an example, according to a programmed input/output (PIO) scheme, the host computer issues commands to the storage device through an adapter. The adapter interrupts the host each time that it is ready to transfer a sector (e.g., 512 bytes) or a multitude of sectors of data. The host controls the transfer of data between the storage device and the memory by issuing instructions. Accordingly, a programmed input/output (PIO) scheme requires significant host resources in order to coordinate and control the transfer of data.
With reference now to FIG. 1, a flow chart illustrating the operation of a prior art adapter in accordance with a programmed input/output (PIO) system or scheme is shown. According to such a system, the host computer writes command parameters to the appropriate task file registers (step 100). The host then writes the command itself to the task file's command register. The task file registers are typically maintained as part of a host to device adapter (step 104). At step 108, a determination is made as to whether the device, for example, a hard disk drive, is ready. If the device is not ready, the system idles at step 108. If the device is ready, the task file status register is updated with a drive ready signal (step 112). In the case of a read from the device, an interrupt is also asserted to the host. Depending on the direction of the transfer, the host or the device writes the data register, until one or more sectors of data are transferred (step 116). After the data has been transferred, the adapter interrupts the host (step 120) to notify the host that the transfer of data has been completed. At step 124, if all commanded data transfers have been completed, the system may return to step 100. If data transfers remain to be completed, the system returns to step 108.
From the above description of a prior art programmed input/output system for transferring data between a host computer and a peripheral storage device, it can be appreciated that such a system consumes a large amount of host computer resources. In particular, a PIO data transfer scheme requires the host computer to write the instructions to commence the operation to the adapter and requires the host computer to monitor the status register to determine when the data transfers can commence. Such implementations requiring interactions with the host are slow. Once the transfer of the data is started, the host or the device writes the data one dword at a time, resulting in a slow rate of transfer. Furthermore, the PIO scheme for transferring the data involves interrupting the host after one or multiple sectors of data have been transferred. In addition to consuming large amounts of host resources, the PIO scheme for transferring data is inefficient, because various components of the system sit idle while waiting for confirmation that other components are ready to perform the data transfers. Accordingly, clock cycles are wasted, and the time required to complete the data transfers is extended.
Another scheme for transferring the data is a direct memory access (DMA) system or scheme. In a direct memory access system, the storage device adapter is provided with the information regarding the location of the data to be transferred and the number of bytes to transfer to or from that location by the host computer. The storage device adapter can then directly access the memory to complete the data transfer. Under such a scheme, fewer host resources are required. However, in existing systems, the storage device controller issues interrupts periodically. In addition, in existing systems, there is a period of latency between receipt of a command to transfer data and actual data transfer.
With reference now to FIG. 2, a flow chart illustrating the operation of a prior art adapter in connection with a direct memory access system is illustrated. Initially, at step 200, the host computer writes the address of the data and the number of bytes for the transfer into the DMA engine registers. Next, at step 204, the host writes the command parameters and the command itself to task file registers in the adapter. At step 208, a determination is made as to whether the peripheral device, such as a hard disk drive, is ready to begin the data transfer. If the device is not ready, the system idles at step 208. If the device is ready, the DMA engine initiates the data transfer. The data is then transferred between the host computer and the peripheral device until the bytes in the DMA byte count register expire (step 216). At step 220, a determination is made as to whether all of the commanded data transfers have been completed. The commanded data transfer may be equal or larger than the bytes programmed in the DMA engine byte count register. If the commanded data transfer is not completed, the device channel interrupts the host at step 224 and transitions to step 228, for the DMA engine to be reprogrammed.
The adapter then returns to step 216 for the new data transfer. If at step 220 all the data transfers have been completed, the device channel interrupts the host (step 232). The data transfer is then complete (step 236).
From the above description of the operation of a prior art DMA scheme, it is apparent that the host computer is required to write commands to the registers associated with the adapter each time a transfer of data is required. Therefore, the host computer is required to expend clock cycles accessing the registers in the adapter to pass commands involving devices connected to the adapter. In addition, it will be noted that data transfers do not occur until confirmation that the device is ready. Accordingly, the components of the prior art system utilizing a DMA scheme are idle until such confirmation is received. The data transfer in a DMA scheme, although an improvement over the PIO scheme, has the additional limitation that the DMA engine byte count may not be sufficient to transfer all the data. If the number of bytes programmed in the DMA engine expire before the transfer of the data is completed, the host is interrupted to program the DMA engine with a new address and byte count. In this situation, the performance of the write operation to the device is limited by how fast the host can reprogram the DMA engine. In this situation, the performance of the read operation can be enhanced by adapters which store the data read from the device until the DMA engine is programmed. Typically the storage is limited and if the adapter's storage becomes full the device is held idle.
Therefore, there is a need for a method and apparatus that improves the exchange of command and status between the host and the adapter. Furthermore, there is need for a method and an apparatus that reduces the overhead in programming of the DMA engine by managing the address and byte count information (referred to as scatter/gather information) and that offloads the host from the flow control of the data exchanged between the host and the adapter. In addition, there is a need for a method and an apparatus that minimizes the number of interrupts that the host is required to service. In addition, there is a need for such a method and an apparatus to reduce the latencies associated between the host and the device.